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GALVANTECH, INC. ASYNCHRONOUS SRAM
FEATURES
* * * * * * * * * * * Fast access times: 9, 10, 12 and 15ns Fast OE# access times: 4, 5, 6 and 7ns Single +3.3V+0.3V power supply Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Easy memory expansion with CE#, CE1#, CE2 and OE# options Automatic chip deselect power down High-performance, low-power consumption, CMOS, double-metal process Low profile 100 pin TQFP and 119 bump, 14mm x 22mm PBGA (Ball Grid Array) packages Multiple Ground and VCC pins for maximum noise immunity
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
128K x 24 SRAM
+3.3V SUPPLY, THREE MEGABIT THREE CHIP ENABLES
GENERAL DESCRIPTION
The GVT73128A24 and GVT73128S24 are organized as a 131,072 x 24 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using triple-layer polysilicon, double-layer metal technology. This device offers multiple power and ground pins for improved performance and noise immunity. For increased system flexibility and eliminating bus contention problems, this device offers multiple chip enables (CE#, CE1# and CE2), and output enable (OE#) with this organization. For GVT73128S24 device in 100-pin TQFP package, separate byte enables (BE0#, BE1#, and BE2#) are also available to control individual bytes. Writing to the device is accomplished by bringing Chip Enables (CE# and CE1#) and Write Enable (WE#) inputs LOW and CE2 HIGH. Reading from the device is accomplished by bringing Chip Enables (CE# and CE1#) LOW and bringing CE2 and Write Enable (WE#) inputs HIGH, along with Output Enable (OE#) being asserted LOW. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.
OPTIONS
* Timing 9ns access 10ns access 12ns access 15ns access Packages 100-pin TQFP 119-lead BGA Temperature Commercial Industrial
MARKING
-9 -10 -12 -15
*
T B
*
None I
(0C to 70C) (-40C to 85C)
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Web Site www.galvantech.com
Rev. 8/99
Galvantech, Inc. reserves the right to chang e products or specifications without notice.
GALVANTECH,
FUNCTIONAL BLOCK DIAGRAM
VCC VSS
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
A0
DQ0
ROW DECODER
ADDRESS BUFFER
MEMORY ARRAY 128K X 24
I/O BUFFER
DQ23
A16
COLUMN DECODER
CONTROL
CE# CE1# CE2 BE0# BE1# BE2# WE# OE#
Note: BE0#, BE1# and BE2# are available for GVT73128S24 only.
August 31, 1999
2
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GALVANTECH,
128Kx24, 119-Bump PBGA (Top View)
1 A B C D E F G H J K L M N P R T U
NC NC
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
128Kx24, 100-PIN TQFP (Top View)
NC NC A11 A12 A13 A14 A15 CE2 VCC VSS CE1# CE# A16 A5 A4 A3 NC NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66
2
3
4
5
6
A4 A3
7
NC NC
A11 A14 A15 A16 A12 A13 CE# CE2 A5
DQ16 NC
NC CE1#
NC DQ0
DQ17 VCC VSS VSS VSS VCC DQ1 DQ18 VSS
VCC
VSS VCC VSS DQ2
DQ19 VCC VSS VSS VSS VCC DQ3 DQ20 VSS
VCC
VSS
VCC
VSS DQ4
DQ21 VCC VSS VSS VSS VCC DQ5
VCC VSS VCC
VSS VCC VSS VCC
DQ22 VCC VSS VSS VSS VCC DQ6 DQ23 VSS
VCC
VSS VCC VSS DQ7
DQ12 VCC VSS VSS VSS VCC DQ8 DQ13 VSS
VCC
VSS VCC VSS DQ9
DQ14 VCC VSS VSS VSS VCC DQ10 DQ15 NC NC NC A10 A9 NC A8 A7 NC
WE#
NC A0 A6
NC DQ11 A1 A2 NC NC
NC VCC VSS DQ16 DQ17 VSS VCC DQ18 DQ19 VSS VCC DQ20 DQ21 VCC NC NC VSS DQ22 DQ23 VCC VSS DQ12 DQ13 VCC VSS DQ14 DQ15 VCC VSS NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC VCC VSS DQ0 DQ1 VSS VCC DQ2 DQ3 VSS VCC DQ4 DQ5 VCC NC NC VSS DQ6 DQ7 VCC VSS DQ8 DQ9 VCC VSS DQ10 DQ11 VCC VSS NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Note: BE0#, BE1# and BE2# are available for GVT73128S24 in 100-pin TQFP package only. For GVT73128A24 in 100-pin TQFP package, pin# 47, 48 and 49 are NC.
August 31, 1999
3
Rev. 8/99
NC NC NC NC A10 A9 A8 A7 OE# VSS VCC WE# A6 A0 A1 A2 BE0# BE1# BE2# NC
Galvantech, Inc. reserves the right to change products or specifications without notice.
OE#
GALVANTECH,
PIN DESCRIPTIONS
TQFP PINS GVT73128A24
44, 87, 35, 94, 45, 46, 85, 86, 43, 38, 37, 36, 98, 97, 96, 95, 88 42
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
TQFP PINS GVT73128S24
44, 87, 35, 94, 45, 46, 85, 86, 43, 38, 37, 36, 98, 97, 96, 95, 88 42
BGA PINS
5T, 6T, 6U, 6A, 5B, 5U, 3T, 2U, 2T, 2B, 3B, 3A, 5A 4T 6B, 3U, 2A, 4A,
SYMBOL
A0-A16
TYPE
Input
DESCRIPTION
Address Inputs: These inputs determine which cell is addressed.
WE#
Input
Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH for a READ cycle. Chip Enable: These inputs are used to enable the device. When CE# and CE1# are LOW and CE2 is HIGH, the chip is selected. When CE# or CE1# are HIGH or CE2 is LOW, the chip is disabled and automatically goes into standby power mode . Byte Enable: These active LOW inputs are available for GVT73128A24 in 100-pin TQFP package only. These active LOW inputs allow individual bytes to be written or read. When BE0# is LOW, the data is written to or read from the lower byte (DQ0-DQ7). When BE1# is LOW, the data is written to or read from the middle byte (DQ8-DQ15). When BE2# is LOW, the data is written to or read from the higher byte (DQ16-DQ23). Output Enable: This active LOW input enables the output drivers .
89, 90, 93
89, 90, 93
4B, 5C, 3C
CE#, CE1#, CE2
Input
-
47, 48,49
-
BE0#, BE1#, BE2#
Input
39 77, 76, 73, 72, 69, 68, 63, 62, 59, 58, 55, 54, 22, 23, 26, 27, 4, 5, 8, 9, 12, 13, 18, 19
39 77, 76, 73, 72, 69, 68, 63, 62, 59, 58, 55, 54, 22, 23, 26, 27, 4, 5, 8, 9, 12, 13, 18, 19
4U 7C, 7D, 7E, 7F, 7G, 7H, 7K, 7L, 7M, 7N, 7P, 7R, 8M, 8N, 8P, 8R, 8C, 8D, 8E, 8F, 8G, 8H, 8K, 8L 1J, 2D, 2F, 2H, 2K, 2M, 2P, 3E, 3G, 3J, 3L, 3N 5E, 5G, 5J, 5L, 5N, 6D, 6F, 6H, 6K, 6M, 6P, 7J 2E, 2G, 2J, 2L, 2N, 3D, 3F, 3H, 3K, 3M, 3P, 4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 4N, 4P, 5D, 5F, 5H, 5K, 5M, 5P, 6E, 6G, 6J, 6L, 6N 1A, 1B, 1T, 1U, 2C, 2R, 3R, 4C, 4R, 5R, 6C, 6R, 7A, 7B, 7T, 7U
OE# DQ0-DQ23
Input
Input/Output SRAM Data I/O: Data inputs and data outputs .
2, 7, 11, 14, 20, 24, 2, 7, 11, 14, 20, 24, 28, 41, 53, 57, 61, 28, 41, 53, 57, 61, 67, 70, 74, 79, 92 67, 70, 74, 79, 92
V CC
Supply
Power Supply: 3.3V
+ 0.3V
3, 6, 10, 17, 21, 25, 3, 6, 10, 17, 21, 25, 29, 40, 52, 56, 60, 29, 40, 52, 56, 60, 64, 71, 75, 78, 91 64, 71, 75, 78, 91
VSS
Groun d
Ground
1, 15, 16, 30, 31, 32, 33, 34, 47, 48, 49, 50, 51, 65, 66, 80, 81, 82, 83, 84, 99, 100
1, 15, 16, 30, 31, 32, 33, 34, 50, 51, 65, 66, 80, 81, 82, 83, 84, 99, 10 0
NC
-
No Connect: These signals are not internally connected. User can connect them to VCC, VSS, or any signal lines or simply leave them floating.
August 31, 1999
4
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GALVANTECH,
TRUTH TABLE
MODE STANDBY STANDBY STANDBY BYTE 0 READ (DQ0-DQ7) BYTE 1 READ (DQ8-DQ15) BYTE 2 READ (DQ16-DQ23) WORD READ (DQa-DQd) WORD WRITE (DQa-DQd) BYTE 0 WRITE (DQ0-DQ7) BYTE 1 WRITE (DQ8-DQ15) BYTE 2 WRITE (DQ16-DQ23) OUTPUT DISABLE
CE # CE1# CE 2
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
WE# X X X H H H H L L L L X H
OE# X X X L L L L X X X X X H
BE0# X X X L H H L L L H H H X
BE1# X X X H L H L L H L H H X
BE2# X X X H H L L L H H L H X
DQ0DQ7 HIGH-Z HIGH-Z HIGH-Z Q HIGH-Z HIGH-Z Q D D HIGH-Z HIGH-Z HIGH-Z HIGH-Z
DQ8DQ15 HIGH-Z HIGH-Z HIGH-Z HIGH-Z Q HIGH-Z Q D HIGH-Z D HIGH-Z HIGH-Z HIGH-Z
DQ16DQ23
POWER
H X X L L L L L L L L L L
X H X L L L L L L L L L L
X X L H H H H H H H H H H
HIGH-Z STANDBY HIGH-Z STANDBY HIGH-Z STANDBY HIGH-Z ACTIVE HIGH-Z Q Q D HIGH-Z HIGH-Z D HIGH-Z HIGH-Z ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Note: BE0#, BE1# and BE2# are available for GVT73128S24 in 100-pin TQFP package only.
August 31, 1999
5
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GALVANTECH,
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V VIN ...........................................................-0.5V to VCC+1.0V Storage Temperature (plastic) ..........................-65 oC to +150o Ambient Temperature ......................................-55o C to +125o Junction Temperature .................................................. +125 o Power Dissipation ...........................................................1.0W Short Circuit Output Current .........................................50mA
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(All Temperature Ranges; VCC = 3.3V +0.3V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage 0V < V IN < VCC Output(s) disabled, 0V < V OUT < VCC IOH = -4.0mA IOL = 8.0mA
CONDITIONS
Data Inputs (DQx ) All Other Inputs
SYMBOL
V I HD V IH V Il IL I IL O V OH V OL VCC
MIN
2.2 2.2 -0.5 -5 -5 2.4
MAX
VCC+0.5 4.6 0.8 5 5
UNITS
V V V uA uA V
NOTES
1, 2 1, 2 1, 2
1 1 1
0.4 3.0 3.6
V V
DESCRIPTION
Power Supply Current: Operating TTL Standby
CONDITIONS
Device selected; CE# < V IL ; VCC =MAX; f= fMAX ; outputs open CE# >V IH; VCC = MAX; f=fMAX
SYM
Ic c ISB1
TYP
80 30
-9
165 55
-10
150 50
-12
130 45
-15
110 40
UNIT S NOTES mA mA 3, 14 14
CMOS Standby
CE1# >VCC -0.2; VCC = MAX; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0
ISB2
5
10
10
10
10
mA
14
CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
TA = 25 o C; f = 1 MHz VCC = 3.3V
SYMBOL
CI CI/O
MAX
6 8
UNITS
pF pF
NOTES
4 4
August 31, 1999
6
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GALVANTECH,
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 3.3V +0.3V)
DESCRIPTION
READ Cycle READ cycle tim e Address access time Chip Enable access time Output hold from address chang e Chip Enable to output in Low- Z Chip disable to output in High-Z Output Enable access time Output Enable to output in Low- Z Output Enable to output in High-Z Byte Enable access tim e Byte Enable to output in Low-Z Byte disable to output in High-Z Chip Enable to power-up time Chip disable to power-down tim e WRITE Cycle WRITE cycle tim e Chip Enable to end of write Address valid to end of write, with OE# HIGH Address setup time Address hold from end of write WRITE pulse width WRITE pulse width, with OE# HIGH Data setup tim e Data hold tim e Write disable to output in Low-Z Write Enable to output in High-Z Byte Enable to end of write
t WC t CW tAW tA S tAH tWP2 tWP1 tDS t DH t LZWE t HZW E tBW t RC tA A t ACE t OH tLZC E tHZC E tAO E t LZOE t HZOE t ABE tLZBE tHZB E tPU tPD
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
-9
SY M MIN MAX
- 10
MIN MAX MIN
- 12
MAX MIN
- 15
MAX UNIT S NOTES
9 9 9 3 3 4 4 0 5 5 0 5 0 9 9 7 7 0 0 9 7 5.5 0 3 5 7
10 10 10 3 3 5 5 0 5 5 0 5 0 10 10 7 7 0 0 9 7 6 0 3 5 7
12 12 12 3 3 6 6 0 6 6 0 6 0 12 12 8 8 0 0 10 8 6 0 4 6 8
15 15 15 3 3 7 7 0 7 7 0 7 0 15 15 9 9 0 0 11 9 7 0 5 7 9
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 7 4, 6, 7 4, 7 4, 6, 7 4 4 4, 6 4, 7 4, 6, 7
August 31, 1999
7
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GALVANTECH,
AC TEST CONDITIONS Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 0V to 3.0V 1.5ns 1.5V 1.5V See Figures 1 and 2
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
OUTPUT LOADS
DQ Z0 = 50 50 Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 DQ 351 5 pF 30 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
1. 2. 3. 4. 5. 6. 7. All voltages referenced to VSS (GND). Overshoot: Undershoot: VIH +6.0V for t t RC /2. VIL -2.0V for t t RC /2
8. 9.
WE# is HIGH for READ cycle. Device is continuously selected. Chip enable and output enables are held in their active state.
Ic c is given with no output current. Ic c increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL =5pF as in Fig. 2. Transition is measured +500mV from steady state voltage. At any given temperature and voltage condition, t HZCE is less than t LZCE and t HZWE is less than tLZWE.
10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a WRITE cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. 14. Typical values are measured at 3.3V, 25o C and 15ns cycle time.
August 31, 1999
8
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GALVANTECH,
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
READ CYCLE NO. 1(8, 9 )
tRC
ADDR
tAA t OH
VALID
Q
PREVIOUS DATA VALID
READ CYCLE NO. 2(7, 8, 10, 12 )
t
DATA VALID
RC
CE# CE1# CE2 BE0# BE1# BE2#
t t ABE t
HZCE
t
AOE
t
HZBE
LZOE
OE#
t
LZBE
t ACE tHZOE
t
LZCE
Q
HIGH Z
DATA VALID DON'T CARE UNDEFINED
Note: BE0#, BE1# and BE2# are available for GVT73128S24 only.
August 31, 1999
9
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GALVANTECH,
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
WRITE CYCLE NO. 1(7, 12, 13) (Write Enable Controlled with Output Enable OE# active LOW))
t WC
ADDR
tAW t CW tAH
CE# CE1# CE2 BE0# BE1# BE2# WE#
tDS tDH tBW
t AS
t WP2
D
tHZWE
DATA VALID
tLZWE
Q
HIGH Z
WRITE CYCLE NO. 2(12, 13) (Write Enable Controlled with Output Enable OE# inactive HIGH)
tWC
ADDR
tAW t CW tAH
CE# CE1# CE2
BE0# BE1# BE2#
tAS
t BW
tWP1
WE#
tDS tDH
D Q
DATA VALID HIGH Z DON'T CARE UNDEFINED
Note: BE0#, BE1# and BE2# are available for GVT73128S24 only.
August 31, 1999
10
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GALVANTECH,
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
WRITE CYCLE NO. 3(12, 13) (Chip Enable Controlled)
t
WC
ADDR
t t
AW
t
t
AH
AS
CW
CE# CE1# CE2
t
BE0# BE1# BE2#
BW
t
WP1
WE#
t
DS
t
DH
D
DATA VALID HIGH Z
DON'T CARE
Q
WRITE CYCLE NO. 4(12, 13) (Byte Enable Controlled)
t WC
ADDR
t AW tAH t BW t AS
BE0# BE1# BE2# CE2 CE# CE1#
t
CW
t WP1
WE#
t
DS
t
DH
D
DATA VALID HIGH Z
DON'T CARE
Q
Note: BE0#, BE1# and BE2# are available for GVT73128S24 only.
August 31, 1999
11
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GALVANTECH,
100 Pin TQFP Package Dimensions
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
16.00 + 0.10 14.00 + 0.10
#1
20.00 + 0.10
22.00 + 0.10
1.40 + 0.05
1.60 Max Note: All dimensions in Millimeters
0.65 Basic
0.30 + 0.08
0.60 + 0.15
August 31, 1999
12
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GALVANTECH,
7 x 17 (119-lead) BGA Dimensions
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
22.00 + 0.20 20.32 1.27
7 6 5 4 3 2 1
14.00 + 0.20
7.62
1.27
UTRP
NML K J
HGF
EDCBA
o 0.75+0.15 (119X)
BOTTOM VIEW
19.50 + 0.10
12.00 + 0.10
0.70 REF.
0.90 + 0.10
30 TYP.
0.56 REF.
0.60 + 0.10
SIDE VIEW
Note: All dimensions in Millimeters
August 31, 1999
13
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
2.40 MAX.
PIN 1A CORNER
TOP VIEW
GALVANTECH,
GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM
Ordering Information for 128K x 24 GVT 73128A24 XX - XX X X
Galvantech Prefix Part Number (No Byte Enable Controls) Temperature (Blank = Commercial I = Industrial) Speed ( 9 = 9ns, 10 = 10ns, 12 = 12ns, 15 = 15ns) Package (T = 100 PIN TQFP, B = 119 BUMP PBGA)
GVT 73128S24 XX - XX X
Galvantech Prefix Part Number (With Byte Enable Controls) Temperature (Blank = Commercial I = Industrial) Speed ( 9 = 9ns, 10 = 10ns, 12 = 12ns, 15 = 15ns) Package (T = 100 PIN TQFP, B = 119 BUMP PBGA)
August 31, 1999
14
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99

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